The present invention relates to a semiconductor process and, more specifically, relates to a barrier structure on the outer edge of bonded wafers including individual die for protection from corrosion and contamination in a three-dimensional (3-D) wafer-to-wafer vertical stack.
Integrated circuits (ICs) form the basis for many electronic systems. Essentially, an integrated circuit (IC) includes a vast number of transistors and other circuit elements that are formed on a single semiconductor wafer or chip and are interconnected to implement a desired function. The complexity of these integrated circuits (ICs) requires the use of an ever increasing number of linked transistors and other circuit elements.
Many modern electronic systems are created through the use of a variety of different integrated circuits; each integrated circuit (IC) performing one or more specific functions. For example, computer systems include at least one microprocessor and a number of memory chips. Conventionally, each of these integrated circuits (ICs) is formed on a separate chip, packaged independently and interconnected on, for example, a printed circuit board (PCB).
As integrated circuit (IC) technology progresses, there is a growing desire for a xe2x80x9csystem on a chipxe2x80x9d in which the functionality of all of the IC devices of the system are packaged together without a conventional PCB. Ideally, a computing system should be fabricated with all the necessary IC devices on a single chip. In practice, however, it is very difficult to implement a truly high-performance xe2x80x9csystem on a chipxe2x80x9d because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits.
As a compromise, various xe2x80x9csystem modulesxe2x80x9d have been introduced that electrically connect and package integrated circuit (IC) devices which are fabricated on the same or on different semiconductor wafers. Initially, system modules have been created by simply stacking two chips, e.g., a logic and memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip structure. Subsequently, multi-chip module (MCM) technology has been utilized to stack a number of chips on a common substrate to reduce the overall size and weight of the package, which directly translates into reduced system size.
Existing multi-chip module (MCM) technology is known to provide performance enhancements over single chip or chip-on-chip (COC) packaging approaches. For example, when several semiconductor chips are mounted and interconnected on a common substrate through very high density interconnects, higher silicon packaging density and shorter chip-to-chip interconnections can be achieved. In addition, low dielectric constant materials and higher wiring density can also be obtained which lead to the increased system speed and reliability, and the reduced weight, volume, power consumption and heat to be dissipated for the same level of performance. However, MCM approaches still suffer from additional problems, such as bulky package, wire length and wire bonding that gives rise to stray inductances that interfere with the operation of the system module.
An advanced three-dimensional (3D) wafer-to-wafer vertical stack technology has been recently proposed by researchers to realize the ideal high-performance xe2x80x9csystem on a chipxe2x80x9d as described in xe2x80x9cFace To Face Wafer Bonding For 3D Chip Stack Fabrication To Shorten Wire Lengthsxe2x80x9d by J. F. McDonald et al., Rensselaer Polytechnic Institute (RPI) presented on Jun. 27-29, 2000 VMIC Conference, and xe2x80x9cCopper Wafer Bondingxe2x80x9d by A. Fan et al., Massachusetts Institute of Technology (MIT), Electrochemical and Solid-State Letters, 2 (10) 534-536 (1999). In contrast to the existing multi-chip module (MCM) technology which seeks to stack multiple chips on a common substrate, 3-D wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance.
One major challenge of 3-D wafer-to-wafer vertical stack integration technology is the metal bonding between wafers and between die in a single chip and the wafer protection from possible corrosion and contamination caused or generated by process steps after the wafers are bonded from reaching active IC devices on the bonded wafers. Therefore, a need exists to erect a barrier structure on the outer edge of bonded wafers and individual die to protect the bonded wafers and die against corrosion and contamination in a three-dimensional (3-D) wafer-to-wafer vertical stack.